The present invention generally relates to an arrangement, system and method for claiming bus transactions, and more specifically, relates to an arrangement, system, and method using memory based I/O decode.
Over time, several I/O bus standards have evolved that specify protocols and interfaces for interfacing peripheral devices. These standards include Industry Standard Architecture (ISA), Extended Industry Standard Architecture (EISA) and other I/O bus standards. Recently, the Peripheral Component Interconnect (PCI) bus has gained wide acceptance as a primary I/O bus in the computer industry. The PCI bus standard provides for high bandwidth and flexibility that is independent of new processor technologies and increased processor speed, and computer system architects have designed large numbers of peripherals such as graphics, accelerators and SCSI disc drive controllers to be utilized with a PCI bus.
Generally, computer systems designed today that incorporate PCI bus capabilities also include a slower, secondary I/O bus (e.g., ISA bus described above) for compatibility with numerous legacy peripheral devices (e.g., floppy disk controllers and keyboard controllers) still existing and/or designed according to the old ISA standards. Many of these peripheral devices are still desired by computer users. Therefore, it is desirable to include, or to be able to incorporate, these existing peripheral devices that are designed to interface with older bus standards into a system that has a PCI bus. Of interest in this regard, a new Low Pin Count (LPC) Interface Specification providing interfacing between legacy I/O devices (e.g., floppy drive controllers and keyboard controllers) and a PCI bus was announced by Intel Corporation on Sep. 29, 1997.
As further relevant discussion, when performing bus transactions in a typical bus or multi-bus system, a master generates a bus transaction and sends it out on a bus (see FIG. 3). Agents on the bus perform a decoding operation on the address of the transaction to determine if the bus transaction is targeted to them (i.e., to determine if they are a target agent). If it is determined that a particular agent is the targeted device, then that agent positively claims the transaction. These types of agents are referred to herein as positive decode agents because they must decode the address of a bus transaction to determine ownership of that particular bus transaction.
The PCI bus standard specification incorporates one exception to positive decoding, i.e., such standard specifies that one agent on the bus may actually claim transactions without performing decoding. This agent is referred to herein as a subtractive decode agent. With regard to the operation of the subtractive decode agent, after all of the positive decode agents on the bus have decoded the address of a transaction and have been given first predetermined times (i.e., xe2x80x9cright of first refusalxe2x80x9d clock cycles) to determine that they do not own the transaction (i.e., see low-transitioning xe2x80x9cfastxe2x80x9d 320, xe2x80x9cmedxe2x80x9d 322 and xe2x80x9cslowxe2x80x9d 324 assertions associated with the FIG. 3 timing chart labelled xe2x80x9c(1) DEVSEL# (FROM POSITIVE DECODE AGENT 303a)xe2x80x9d), the subtractive decode agent automatically claims ownership of the transaction by default at occurrence of a second predetermined time (i.e., see lowtransition xe2x80x9csubtractivexe2x80x9d 340 assertion associated with the FIG. 3 timing chart labelled xe2x80x9c(2) DEVSEL# (FROM SUBTRACTIVE DECODE AGENT 303b)xe2x80x9d).
Art which may be relevant to the present invention may be found in: U.S. Pat. No. 5,568,621 issued Oct. 22, 1996, to Wooten; U.S. Pat. No. 5,621,900 issued Apr. 15, 1997 to Lane et al.; and xe2x80x9cPentium Pro Family Developer""s Manual, Volume 2: Programmer""s Reference Manualxe2x80x9d, pp. 8-5 through 8-6 (undated).
Subtractive decode agents may be bus bridges that interface the PCI bus to a bus operating according to a standard or set of protocols different than that associated with the PCI bus. Because the PCI bus standard only allows one subtractive decode agent on the bus, a computer system that incorporates a subtractive decode agent as a bus bridge limits the number of non-PCI buses that may be supported. For example, unless special accommodations are provided, the FIG. 1 system (discussed in greater detail ahead) would not be able to have two ISA busses, i.e., could not have both of an ISA bus 103 (provided as a peripheral bus within a desk-top computing system) and an ISA bus 117 (provided as a bus within a docked notebook computing system). It is desirable to be able to have a computer system that incorporates a PCI or other standard bus with more than one bus of a different standard.
Another disadvantage is that since there are multiple differing agents and differing agent locations on typical buses, a plurality of predetermined clock cycles (i.e., the xe2x80x9cfastxe2x80x9d, xe2x80x9cmedxe2x80x9d, xe2x80x9cslowxe2x80x9d and xe2x80x9csubtractivexe2x80x9d cycles discussed above) are required to accommodate all such differing agents and locations, and redundant logic resources (e.g., logical gates, comparators, etc.) are required within the differing agents/locations for performing the decoding. A still further disadvantage is that since claiming of a PCI subtractive decoding takes the most clock signals to claim a transaction, a system having to wait for and accommodate subtractive decoding is slowed as extra clock cycles added by each subtractive decoding operation accumulate during operation of the system.
The present invention overcomes the above-mentioned limitations with respect to the background art. More particularly, the present invention relates to an input/output (I/O) decode arrangement including an I/O decode map in a form of a memory block and containing, before start of any bus I/O transactions, I/O address decode information useable for I/O address decoding for bus transaction ownership, for at least a portion of possible I/O addresses in a system.